The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, traditional photolithography alone can no longer meet the requirements for critical dimension (CD) and pattern density in advanced process nodes, such as 10 nanometer (nm) or smaller. Frequently, a spacer technique is used for doubling the exposed pattern in advanced photolithography. That is, the pitch of a final pattern is reduced to only half compared with the first exposed pattern. In a typical spacer technique, a mandrel pattern is formed using photolithography, and a spacer is formed around the mandrel pattern. Subsequently, the mandrel pattern is removed, and the spacer is partially removed by a photolithography cut process. The final pattern includes the remaining portion of the spacer, and/or its derivative. Frequently, the parameters of the final pattern (e.g., CD, pitch, and spacing) are measured for process control purposes. However, the final pattern is usually just a set of long parallel lines and it is difficult to map the dimensions of the final pattern back to the various steps in the pattern formation process.